1. Field of Invention
The present invention relates to a method for manufacturing integrated circuits. More particularly, the present invention relates to a method for manufacturing dynamic random access memory (DRAM).
2. Description of Related Art
As the microprocessor of a computer becomes more powerful and the size of software programs increase, the demand for a high capacity capacitor in each memory unit is greater. Following the recent increase in integration level for DRAMs, each memory cell now comprises just a transfer field effect transistor and a storage capacitor.
Since a capacitor is the storage center of a DRAM cell, the higher the electric charges stored within a capacitor, the lower the effect of noise on the data reading is. The most common methods of increasing the electric charge storage capacity of a capacitor include increasing the surface area, choosing a material having a high dielectric constant to form the dielectric film layer, or reducing the thickness of the dielectric film layer.
At present, high dielectric constant materials that can be used to form the dielectric film layer include tantalum pentoxide Ta.sub.2 O.sub.5, Lead-Zirconium-Titanium oxide Pb(Zr,Ti)O.sub.3 (PZT), and barium-strontium-titanium oxide (Ba,Sr)TiO.sub.3 (BST). Due to the increase in the level of integration for integrated circuits, surface area of a capacitor can only be increased by developing three-dimensional capacitor structures, for example, stacked type or trench type capacitors. For even higher level of integration such as 64 Mb DRAM, the electrode and the dielectric film layer of the capacitor not only extend in a horizontal direction, but also stacked up vertically to form what is known as a fin-type capacitor. Alternatively, the electrode and the dielectric film layer of the capacitor extend to form vertical structure known commonly as a cylindrical-type capacitor.
FIG. 1 is a schematic, cross-sectional diagram showing a conventional cylindrical type capacitor for a DRAM cell. The method of forming the DRAM capacitor includes the steps of first providing a substrate 100 having some isolation regions 102 already formed therein. Next, field effect transistors 104 are formed on the substrate 100, and then a dielectric layer 110 is formed over the substrate 100. Thereafter, contact openings 112 are formed in the dielectric layer 110, exposing a portion of the source/drain region 108. In the subsequent step, an amorphous silicon layer 114 is formed over the dielectric layer 110, filling the contact openings 112 as well. Next, photolithographic and etching operations are conducted in sequence to pattern the amorphous silicon layer 114 above the dielectric layer 110, and hence forming the lower electrode structure of the capacitor. Thereafter, hemispherical grains (HSG) (not shown in the figure) are selectively formed on the surface of the amorphous silicon layer 114 so that surface area of the lower electrode is increased. Finally, a dielectric film layer 116 is formed over the amorphous silicon layer, and then a polysilicon layer 118 that serves as the upper electrode of the capacitor is deposited over the dielectric film layer 116.
To increase the memory holding capacity of each high-density DRAM cell even further, a thicker layer of amorphous silicon is usually deposited. Since an increase in thickness of the amorphous silicon layer can increase the surface area of the lower electrode, the charge storage capacity of the capacitor is also increased.
However, amorphous silicon has a rather low rate of deposition. At present, choosing the production of DRAMs as an example, depositing amorphous silicon to a thickness of about 8000 .ANG. requires roughly 16 hours. Hence, trying to increase the storage capacity of a capacitor by increasing the thickness of the amorphous silicon layer requires a longer depositing time. Therefore, throughput of production is reduced and cost of operating the oven is increased as well. In addition, a thicker amorphous silicon layer increases the difficulties of patterning the layer in an etching operation.
In light of the foregoing, there is a need to improve the method for manufacturing DRAM cells.